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| Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer Product Features * * * * * * * * * * 110MHz Clock Support TM Supports PowerPC , Intel and RISC Processors 9 Clock Outputs: drive up to 18 loads LVPECL Reference Input Clock Output Disable Control Spread Spectrum Compatible 3.3V Power Supply Pin Compatible with MPC953 Industrial Temp. Range: -40C to +85C 32-Pin TQFP Package Frequency Table BYPASS# PLL_EN VCO_SEL Q(0:7) 0 0 0 REF 0 0 1 REF 0 1 0 REF 0 1 1 REF 1 0 0 REF/4 1 0 1 REF/8 1 1 0 VCO/4 1 1 1 VCO/8 Table 1 FB_OUT REF REF REF REF REF/4 REF/8 VCO/4 VCO/8 Function Table BYPASS# MR/OE# VCO_SEL PLL_EN `1' = PLL Enabled `0' = PLL Bypass `1' = Outputs Disabled HiZ `0' = Outputs Enabled `1' = VCO/2 `0' = VCO `1' = Select VCO `0' = Select PECL_CLK Table 2 Block Diagram Pin Configuration VCO_SEL BYPASS# FB_OUT PLL_EN VDDC 27 VSS VSS 25 24 23 22 21 20 19 18 17 16 FB_OUT 32 31 30 29 28 PECL_CLK PECL_CLK# FB_IN Phase Detector VCO 200-500M LPF /4 /2 7 Q(0:6) Q7 VCO_SEL BYPASS# MR/OE# PLL_EN VDD FB_IN NC NC NC NC VSS PECL_CLK 1 2 3 4 5 6 7 8 9 26 Q0 Z9953 10 11 12 13 14 15 Q1 VDDC Q2 VSS Q3 VDDC Q4 VSS PECL_CLK# VSS Q7 Q6 MR/OE# VDDC Figure 1 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07086 Rev. *A VDDC Q5 06/18/2001 Page 1 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer Pin Description PIN 8 9 12, 14, 16, 18, 20, 22, 24, 26 28 NAME PECL_CLK PECL_CLK# Q(7:0) PWR I/O I I O Description PECL Input Clock. PECL Input Clock. Clock Output. VDDC FB_OUT VDDC O 2 10 FB_IN MR/OE# I I 30 PLL_EN I 31 32 11, 15, 19, 23, 27 1 7, 13, 17, 21, 25, 29 3, 4, 5, 6 BYPASS# VCO_SEL VDDC VDD VSS NC I I Feedback Clock Output. Connect to FB_IN for normal operation. A bypass delay capacitor at this output will control Input Reference / Output phase relationships. Feedback Clock Input. Connect to FB_OUT for accessing the PLL. Master Reset/Output Enable Input. When asserted high, resets all of the internal flip-flops and also disables all of the outputs. When pulled low, releases the internal flip-flops from reset and enables all of the outputs. PLL Select Input. When asserted high, VCO output is selected. And when set low, PECL_CLK is the input to the output dividers. PLL Enable Input. When high, PLL is enabled and when low, PLL is bypassed. VCO Divider Select Input. When set high, VCO output is divided by 2. When set low, the divider is bypassed. 3.3V Power Supply for Output Clock Buffers. 3.3V Power Supply for PLL Common Ground No Connection PD = Internal Pull-Down, PU = Internal Pull-Up. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07086 Rev. *A 06/18/2001 Page 2 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer Maximum Ratings Maximum Input Voltage Relative to VSS: VSS - 0.3V Maximum Input Voltage Relative to VDD: VDD + 0.3V Storage Temperature: Operating Temperature: Maximum ESD protection Maximum Power Supply: Maximum Input Current: -65C to + 150C -40C to +85C 2KV 5.5V 20mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout) Characteristic Input Low Voltage Input High Voltage Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Output Low Voltage Output High Voltage Quiescent Supply Current PLL Supply Current Input Capacitance Symbol VIL VIH IIL IIH VPP VCMR VOL VOH IDDC IDD Cin VDD0.6 15 20 20 4 Min VSS 2.0 Typ Max 0.8 VDD -120 120 1000 VDD0.6 0.6 Units V V A A mV V V V mA mA pF IOL = 20mA, Note 3 IOH = -20mA, Note 3 All VDDC and VDD VDD only Conditions Note 1 Note 2 300 VDD1.5 - VDD = VDDC = 3.3V 5%, TA = -40C to +85C Note 1: Inputs have pull-up, pull-down resistors that affect input current. Note 2: The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. Note 3: Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Output buffers are dual staged to control drive strength in order to reduce over/under shoot. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07086 Rev. *A 06/18/2001 Page 3 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer AC Parameters1 SYMBOL Tr / Tf Fref FrefDC Fvco Tlock Tr / Tf Fout PARAMETER TCLK Input Rise / Fall Reference Input Frequency Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time 2 MIN 25 25 200 4,5 TYP MAX 3.0 110 75 500 10 1.0 110 62.5 200 UNITS ns MHz % MHz ms ns MHz CONDITIONS Output Clocks Rise / Fall Time 0.10 50 25 0.8V to 2.0V VCO_SEL = `0' VCO_SEL = `1' Bypass Mode Maximum Output Frequency FoutDC TCCJ TSKEW Tpd tpZL, tpZH tpLZ, tpHZ Tpd Output Duty Cycle 4,5 45 50 55 100 % ps ps ps ns ns ns Cycle to Cycle Jitter (peak to 4,5 peak) Any Output to Any Output Skew Input to FB_IN Delay (PLL 3,4,5 locked) Output enable time (all outputs) Output disable time (all outputs) Input to Q Delay (PLL bypassed) 3 4,5 -75 - 250 125 6 7 7 VDD = VDDC = 3.3V +/- 5%, TA = -40C to +85C Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. Note 2: Maximum and minimum input reference is limited by the VCO lock range. Note 3: The Tpd (PLL locked) is input reference frequency dependent. Note 4: Driving series or parallel terminator 50 (or 50 to VDD/2) transmission lines. Note 5: Outputs loaded with 30pF each Description The Z9953 is a PLL based clock generator that provides low skew and low jitter clock outputs for high performance systems. The Z9953 features a differential PLL to minimize cycle-to-cycle and phase jitter. The PLL is ensured stable operation given that the VCO is configured to run between 200MHz and 500MHz. The input reference is a differential LVPECL clock. All other control inputs are LVCMOS/LVTTL compatible The Z9953 features 9 LVCMOS/LVTTL compatible outputs each capable of driving two series terminated 50 transmission lines. With this capability the Z9953 has an effective fan-out of 1:18. The outputs can also be tri-stated when MR/OE# is set high. When used as a zero-delay buffer any of the 9 outputs can be used as the feedback input to the PLL. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07086 Rev. *A 06/18/2001 Page 4 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer 32 Pin TQFP Outline Dimensions D SYMBOL A A1 A2 D1 10 A1 A2 A L e b D D1 b e L 0.018 MIN 0.002 0.037 0.012 INCHES NOM 0.354 0.276 0.031 BSC 0.030 0.45 MAX 0.047 0.006 0.041 0.018 MIN 0.05 0.95 0.30 MILLIMETERS NOM 9.00 7.00 0.80 BSC 0.75 MAX 1.20 0.15 1.05 0.45 Ordering Information Part Number Package Type Production Flow Z9953AA 32 PIN TQFP Industrial, -40C to +85C Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress Z9953AA Date Code, Lot # Z9953AA Package A = TQFP Revision Device Number Notice Cypress Semiconductor Corp. reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corp. assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corp. for the use of its products in the life supporting and medical applications Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07086 Rev. *A 06/18/2001 Page 5 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer Document Title: Z9953 3.3V 180 MHz, Multi-Output Zero Delay Buffer Document Number: 38-07086 Rev. ECN No. ** 107122 *A 108065 Issue Date 06/05/01 07/03/01 Orig. of Change IKA NDP Description of Change Convert from IMI to Cypress Changed Commercial to Industrial (See page 5) Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07086 Rev. *A 06/18/2001 Page 6 of 6 |
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